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FAN8006D3
Features
* * * * * * 4-Channel BTL (Balanced transformer-less) driver Built-in thermal shutdown circuit Built-in power save circuit Separated power supply Operating supply voltage: 4.5V ~ 13.2V Corresponds to 3.3V or 5V DSP
Target Application
* Compact disk player * Digital video disk player * Compact disk ROM
(c)2002 Fairchild Semiconductor Corporation
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Description
The FAN8006D3 is a monolithic integrated circuit, suitable for 4-CH motor driver which drives focus actuator, tracking actuator, sled motor and loading motor of a CD-media system. 28-SSOPH-375SG2
Ordering Information
Device Package Ope. Temp. -35C ~ +85C -35C ~ +85C FAN8006D3 28-SSOPH-375SG2
FAN8006D3TF 28-SSOPH-375SG2
Rev. 1.0.0
2
BIAS 28 1 2 26 3 4 5 6 7 25 24 23 22 27 FIN(GND) PreVcc OPIN1(+) OPIN1(-) OPIN4(+) OPIN4(-) OPOUT4 OPOUT1 IN2 OPIN3(+) OPIN3(-) OPOUT3 MUTE STBY2 FIN(GND) 8 9 10 PowVcc CH2 VO2(-) VO2(+) VO1(-) VO1(+) 11 12 13 14 PowVcc CH1 GND
FAN8006D3
FAN8006D3 Pin Assignments
FAN8006D3
21 20 19 18 17 16 15
GND
STBY1 PowVcc3 CH3/4 VO3(-) VO3(+)
VO4(-) VO4(+)
FAN8006D3
Pin Definitions
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Pin Name BIAS OPIN1(+) OPIN1(-) OPOUT1 IN2 MUTE STBY2 GND PowVcc1 CH1 PowVcc2 CH2 VO2(-) VO2(+) VO1(-) VO1(+) VO4(+) VO4(-) VO3(+) VO3(-) PowVcc3 CH3/4 STBY1 GND OPOUT3 OPIN3(-) OPIN3(+) OPOUT4 OPIN4(-) OPIN4(+) PreVcc I/O I I I O I I I O O O O O O O O I O I I O I I Bias voltage input Op-amp CH1 input (+) Op-amp CH1 input (-) Op-amp CH1 output CH2 input CH1 mute control when STBY1 is logic high CH2 standby control Signal ground BTL CH1 power supply BTL CH2 power supply Drive2 output (-) Drive2 output (+) Drive1 output (-) Drive1 output (+) Drive4 output (+) Drive4 output (-) Drive3 output (+) Drive3 output (-) BTL CH3/4 power supply Input for CH1/3/4 standby control Ground Op-amp CH3 output Op-amp CH3 input (-) Op-amp CH3 input (+) Op-amp CH4 output Op-amp CH4 input (-) Op-amp CH4 input (+) Vcc for pre block Pin Function Description
3
FAN8006D3
Internal Block Diagram
PowVcc3 CH3/4
OPIN3(+)
OPIN4(+)
OPIN4(-)
OPIN3(-)
OPOUT4
OPOUT3
PreVcc
VO3(-)
VO3(+)
28
27
26
25
24
23
22
21
GND
FIN (GND)
20
19
18
17
16
15
+
-
+
- 10k 10k 10k 10k TSD 20k - 10k LEVEL SHIFT -
+ +
-+ -+
-
10k
+ +
-+ -+
20k 10k +-
10k +-
+ PowVcc CH3/4
- LEVEL SHIFT
+ PowVcc CH3/4
10k 20k 10k
PowVcc CH2 - 20k 10k
LEVEL SHIFT + 10k
PowVcc CH1 - 10k
LEVEL SHIFT + 10k - 10k +
10k
1 BIAS
2 OPIN1(+)
3 OPIN1(-)
4 OPOUT1
5 IN2
6 MUTE
7 STBY2 (GND) FIN
8 GND
9 PowVcc CH1
10 PowVcc CH2
10k
11 VO2(-)
12 VO2(+)
10k
- ++ -
-
+
-
+
-
+
13 VO1(-)
14 VO1(+)
4
VO4(+) 10k
VO4(-)
STBY1
10k
+- +-
FAN8006D3
Equivalent Circuits (Continued)
POWER OUTPUT
28 9 10 19
CHANNEL OPAMP INPUT
11 12 13 14 15 16 17 18 2 24 27
28
2K 1K
2K
28 3
25
1K
25
23 26
CHANNEL OP-AMP OUTPUT
28 20K 20K 28
BIAS INPUT
28
10K 1 27p 25
25
20K 4 22 25
CHANNEL 2 INPUT
28 28 20K 20K 28
STANDBY 1/2 INPUT
28 1K 20K 28
25 7 25 5 10K 40K 100K 80K 40K
25 20
20K
20K
20K
1K
20K
1K
1K
40K
40K
20K
100K
5
FAN8006D3
Equivalent Circuits
MUTE INPUT
28
6 25
40K
1K
1K
6
30K
1K
FAN8006D3
Absolute Maximum Ratings ( Ta=25C)
Parameter Maximum supply voltage Power dissipation Operating temperature range Storage temperature range
NOTE: Pd is measured base on the JEDEC/STD(JESD 51-2)
Symbol PreVccmax PD TOPR TSTG
Value 15 2.5
note
Unit V W C C
-35 ~ +85 -55 ~ +150
Epoxy board
Pd=2.5W
1. Test PCB is single layer PCB which has only 1 signal plane. PCB size is 76mm x 114mm x 1.6mm. 2. Power dissipation is reduced for using above Ta=25C. It's slope is -20.0mW/C. 3. Do not exceed PD and SOA (Safe Operating Area).
Pd (mW)
2,000 1,500 SOA
500 0 0
25
50
75 85 100
125
150
175
Ambient temperature, Ta [C]
Recommended Operating Conditions ( Ta=25C)
Parameter Supply voltage Supply voltage Supply voltage Supply voltage Symbol PreVcc PowVcc CH1 PowVcc CH2 PowVcc CH3/4 Min. 4.5 4.5 4.5 4.5 Typ. Max. 13.2 PreVcc PreVcc PreVcc Unit V V V V
7
FAN8006D3
Electrical Characteristics
(Unless otherwise specified, Ta=25C, PreVcc=12V, PowVcc CH1=PowVcc CH3/4=5V, PowVcc CH2=12V, RL=8,24) Parameter Quiescent current1 Quiescent current2 Quiescent current3 Quiescent current4 Quiescent current5 Mute on voltage Mute off voltage STBY1 on voltage STBY1 off voltage STBY2 on voltage STBY2 off voltage BTL DRIVE CIRCUIT Channel 1,3,4(RL=8) Output offset voltage 1,3,4 Maximum output voltage 1,3,4 Closed loop voltage gain 1,3,4 Ripple rejection ratio 1,3,4 Slew rate 1,3,4 Channel 2(RL=24) Output offset voltage 2 Maximum output voltage 2 Closed loop voltage gain 2 Ripple rejection ratio 2 Slew rate 2 INPUT OP-AMP Input offset voltage Input bias current High level output voltage Low level output voltage Output sink current Output source current Open loop voltage gain Ripple rejection ratio Slew rate Common mode rejection ratio Common mode input range VOFOP IBOP VOHOP VOLOP ISINK ISOURCE GVO RROP SROP CMRR CMIR PreVcc=5V, RL= PreVcc=5V, RL= PreVcc=5V, RL=50 PreVcc=5V, RL=50 VIN = -75dB, 1KHz VIN = 120KHz, 2VPP VIN = -20dB, 120Hz VIN = -20dB, 1KHz PreVcc=5V -10 4.5 3 2 -0.3 75 60 1 80 +10 400 0.5 4 mV nA V V mA mA dB dB V/s dB V VOF2 VOM2 GVC2 RR2 SR2 -50 9.5 17 10.5 18 60 1 +50 19 mV V dB dB V/s VOF1,3,4 VOM1,3,4 GVC1,3,4 RR1,3,4 SR1,3,4 -50 3.6 17 4.0 18 60 1 +50 19 mV V dB dB V/s Symbol ICC1 ICC2 ICC3 ICC4 ICC5 VMON VMOFF VSTON1 VSTOFF1 VSTON2 VSTOFF2 Conditions
STBY1,2=0.5V,Mute=2V,RL= STBY1,2=2V,Mute=0.5V,RL= STBY2=2V, STBY1,Mute=0.5V STBY2=0.5V, STBY1,Mute=2V STBY2,Mute=0.5V,STBY1=2V,
Min. 2.0 2.0 2.0
Typ. 0.1 22.0 5.5 12.0 17.5 -
Max. 1 31.0 8.5 17.0 24.5 0.5 0.5 0.5 -
Unit mA mA mA mA mA V V V V V V
-
8
FAN8006D3
Application Information
1. Standby/Mute Input
FAN8006D3 have 2 independent standby inputs that is , pin #7(STBY2) and pin #20(STBY1), and 1 independent mute input(pin #7). The digital logics of these functions are as below. STBY1=>Low Mute=>Low CH 1 CH3/4 CH2 Mute=>High STBY1=>High Mute=>Low operate Mute=>High high impedance operate STBY2 High Low -
standby
operate standby
2. Mute Timing Chart
If the mute input(pin #6) voltage rises above 2.0V, the output(CH1) current can be muted under normal operating conditions, make sure to open pin #7 or pull it down below 0.5V. Below figure is high impedance mute timing chart.
Voltage 2[V] Mute(pin #6) 0
PreVcc = 12V PowVcc CH1= 5V BIAS = 1.65V RL = 8 Tm 125sec
time Tm
Voltage Vom
Vout (pin#13,14)
0.5[mV] 0 time
9
FAN8006D3
3. CH2 Drive Output Schematic
Inside IC
Power amp 10K - - + + 10K
10K
PowVccCH2 R
PowVccCH2 20K - +
* The reference voltage BIAS is given externally through pin 1. * The input signal is amplified by (20K/10K) times and then fed to the current conveyor type 2 circuit and the power amp circuit. * The power amp circuit produces the differential output voltages and drives two output power amplifier circuits. * Since the differential gain of the power amplifier is equal to 2 x (1+10K / 10K) , the output signal of the input OP-amp is amplified totally 8. * If the total gain is insufficient or large, external resistor can be used to adjust the gain.
10
+
10
R
- Current Conveyor Type 2
1 Bias
10K
5
10K
-
11 DO
M
DO+ 12
FAN8006D3
4. CH1/3/4 Drive Output Schematic
Inside IC
Power amp 10K - - + + 10K
10K
PowVccCH1 (PowVccCH3/4)
R
1 Bias
2 24 27
* The reference voltage BIAS is given externally through pin 1. * The input OP-amp output signal is amplified by (20K/10K) times and then fed to the current conveyor type 2 circuit and the power amp circuit. * The power amp circuit produces the differential output voltages and drives two output power amplifier circuits. * Since the differential gain of the power amplifier is equal to 2 x (1+10K / 10K) , the output signal of the input OP-amp is amplified totally 8. * If the total gain is insufficient or large, the input OP-amp and the external resistors can be used to adjust the gain.
-
+
-
+
+
9 19
R
- Current Conveyor Type 2
PowVccCH1 (PowVccCH3/4) 20K
10K
10K 3 23 26 4 22 25
-
13 16 18 DO
M
DO+
14 15 17
11
FAN8006D3
Application Circuits
(Voltage control mode)
BIAS VOLTAGE 1 BIAS SERVO AMP FOCUS SLED TRACKING LOADING MUTE STBY2 2 OPIN1(+) 3 OPIN1(-) 4 OPOUT1 5 IN2 6 MUTE 7 STBY PreVcc 28 12V OPIN4(+) 27 OPIN4(-) 26 OPOUT4 25 OPIN3(+) 24 OPIN3(-) 23 OPOUT3 22
FAN8006D3
8 GND 9 PowVcc CH1 GND 21 STBY1 20 STBY1
10 PowVcc CH2 PowVcc CH3/4 19 11 VO2(-) 12 VO2(+) 13 VO1(-) TRACKING ACTUATOR 14 VO1(+) VO3(-) 18 SLED MOTOR VO3(+) 17 VO4(-) 16 VO4(+) 15
LOADING MOTOR
FOCUS ACTUATOR
12
FAN8006D3
13
FAN8006D3
DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the
www.fairchildsemi.com
6/24/02 0.0m 001 Stock#DSxxxxxxxx 2002 Fairchild Semiconductor Corporation

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